The disclosed embodiments relate to a semiconductor device and, more particularly, to a semiconductor device in which a top surface of an upper insulating layer provided on a non-active surface of a semiconductor chip is coplanar with a top surface of a connection pad.
The desire for light, small, high-speed and high-performance electronic products has increased with the development of the electronics industry. Thus, research has been conducted to improve performance of semiconductor packages. In particular, to improve the performance of semiconductor packages, through via techniques (e.g., a through silicon via (TSV) technique, or through substrate via technique) have been developed instead of a conventional wire bonding technique. When vias penetrating a substrate are used, lengths of interconnections connecting semiconductor chips may be reduced. As a result, it is possible to improve performance of a three-dimensional semiconductor package. In addition, the vias may have widths of several micrometers, and thus a large number of vias may be formed in semiconductor chips.